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MG580225 ATPG Clock Control Logic Appnote v2013 3 LPCT OCC

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  Mentor Graphics Confidential 1 September 2013   AppNote MG580225 A Practical Clock Control Circuit Design & Example Tessent  ®   ATPG Test Case October 2013 ©Copyright Mentor Graphics Corporation 1995-2013. All rights reserved. This document contains information that is proprietary to Mentor Graphics ® Corporation. The srcinal recipient of this document may duplicate this document in whole or in part for internal business purposes only, provided that this entire notice appears in all copies in duplicating any part of this document, the recipient agrees to make every reasonable effort to prevent the unauthorized use and distribution of the proprietary information. Trademarks that appear in Mentor Graphics product publications that are not owned by Mentor Graphics are trademarks of their respective owners.  Mentor Graphics Confidential 2 September 2013   Table of Contents 1.   Introduction .............................................................................................................. 5   2.   Clock Control Circuit Description ................................................................................. 5   2.1.   Design Placement .............................................................................................. 5   2.2.   Schematic ......................................................................................................... 6   2.3.   Scan Enable Synchronization ............................................................................... 7   2.4.   Clock Gater Cells ............................................................................................... 7   2.5.   Clock Definition for ATPG .................................................................................... 7   2.6.   Shift Register Block ............................................................................................ 8   2.7.   Clock Control Operation Modes ............................................................................ 9   2.7.1. Functional Mode ......................................................................................................... 9   2.7.2. Shift Mode ................................................................................................................. 9   2.7.3. Slow Capture Mode....................................................................................................10   2.7.4. Fast Capture Mode ....................................................................................................10   2.8.   Timing Diagrams ................................................................................................ 10   2.9.   RTL Description ................................................................................................. 12   3.   Test Case Description................................................................................................ 14   3.1.   Test Case Design Statistics ................................................................................. 14   3.2.   Directory Structure.............................................................................................. 14   3.3.   Test Case Steps................................................................................................. 15   3.4.   RTL Simulation .................................................................................................. 15   3.5.   RTL Synthesis ................................................................................................... 16   3.6.   Baseline ATPG .................................................................................................. 16   3.7.   Clock Control Logic Insertion................................................................................ 16   3.8.   Slow Capture ATPG ............................................................................................ 18   3.8.1.    ATPG Commands ........................................................................................... 18   3.8.2.   Test Procedure File ......................................................................................... 20   3.9.   Fast Capture ATPG ............................................................................................ 23   3.10.   Pattern Verification.......................................................................................... 24    Mentor Graphics Confidential 3 September 2013  3.11.   Compression Logic Insertion and ATPG ............................................................. 25    Appendix A  –  Using OCC in an LPCT flow ............................................................................ 27   1.   Introduction .............................................................................................................. 27   2.   Clock Control Circuit Description ................................................................................. 27   2.1.   Design Placement .............................................................................................. 27   2.2.   Schematic ......................................................................................................... 27   2.3.   Capture Enable Synchronization ........................................................................... 29   2.4.   Clock Gater Cells ............................................................................................... 29   2.5.   Clock Definition for ATPG .................................................................................... 29   2.6.   Shift Register Block ............................................................................................ 30   2.7.   Clock Control Operation Modes ............................................................................ 31   2.7.1. Functional Mode ........................................................................................................31   2.7.2. Shift Mode ................................................................................................................31   2.7.3. Slow Capture Mode....................................................................................................32   2.7.4. Fast Capture Mode ....................................................................................................32   2.8.   Timing Diagrams ................................................................................................ 32   2.9.   RTL Description ................................................................................................. 34   3.   Test Case Description................................................................................................ 36   3.1.   Test Case Design Statistics ................................................................................. 36   3.2.   Directory Structure.............................................................................................. 36   3.3.   Test Case Steps................................................................................................. 37   3.4.   RTL Synthesis ................................................................................................... 37   3.5.   Test logic and clock control insertion ..................................................................... 38   3.6.   Generating, inserting and synthesizing LPCT and TestKompress logic ....................... 40   3.7.   Generating patterns ............................................................................................ 41   3.7.1.   Dofile for pattern generation .............................................................................. 42   3.7.2.   Test Procedure File ......................................................................................... 42   3.7.3.   Slow Capture ATPG ........................................................................................ 42   3.7.4.   Fast Capture ATPG ......................................................................................... 43    Mentor Graphics Confidential 4 September 2013  3.8.   Pattern Verification ............................................................................................. 43  
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