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Silicon nanowires with lateral uniaxial tensile stress profiles for high electron mobility gate-all-around MOSFETs

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Silicon nanowires with lateral uniaxial tensile stress profiles for high electron mobility gate-all-around MOSFETs
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  Silicon nanowires with lateral uniaxial tensile stress profiles for high electronmobility gate-all-around MOSFETs M. Najmzadeh a, * , L. De Michielis a , D. Bouvet a , P. Dobrosz b , S. Olsen b , A.M. Ionescu a a Nanoelectronic Devices Laboratory, Swiss Federal Institute of Technology (EPFL), CH-1015 Lausanne, Switzerland b Newcastle University, School of Electrical, Electronics and Computer Engineering, Newcastle, UK  a r t i c l e i n f o  Article history: Received 14 September 2009Received in revised form 5 November 2009Accepted 8 November 2009Available online 12 November 2009 Keywords: Local oxidationLocal lateral uniaxial tensile stressLocal mobility enhancementGate-all-aroundStrain engineeringSi nanowires a b s t r a c t In this work we present for the first time correlation of lateral uniaxial tensile strain and  I  – V   character-isticsofGAASiNWn-MOSFET, all measuredonthesamedevice. Micro-Ramanspectroscopyisemployedfor direct strain measurement on devices to exploit the main sources of process-induced strain, found tobe accumulation of mechanical potential energy in the Si NWs during local oxidation and releasing it inthe form of local lateral uniaxial tensile stress in the Si NW by out-of-plane mechanical buckling as wellas lateral in-plane elongation during stripping the hard mask and the grown oxide.A triangular GAA Si NW with 0.6GPa peak of lateral uniaxial tensile stress, fabricated using this bulktop-down technology, exhibits promising improvements e.g. of the normalized drain current ( I  D = W  eff  )up to 38%, of the transconductance (  g  m = W  eff  ) up to 50%, of the low field mobility by 53% with a peakof 64% in the peak stress region, compared to a reference device. The mobility extraction srcinally takesinto account the measured strain profile in the channel.   2009 Elsevier B.V. All rights reserved. 1. Introduction Strain engineering has been used for the 90nm technologynode and beyond to enhance the device performance duringaggressive CMOS downscaling. It has been shown that uniaxialcompressive and uniaxial tensile stresses along the  h 110 i  channelorientation with (100) channel surface are the most helpful stres-ses to provide higher mobility of carriers in pMOS and nMOS de-vices, respectively [1]. For planar devices, several local strainengineering techniques e.g. embedded epitaxial films in the S/D,CESL and stress memorization technique (SMT) have been usedto induce uniaxial tensile or compressive stress along the channel[1,2].However,scalabilityofthelocalstressortechnologiesparallelto the scalability of the channel is an issue.Due to having the best possible electrostatistics in multi-gatedevices e.g. Fin-FET and gate-all-around (GAA) devices and there-fore, improved subthreshold slope, immunity to the issues regard-ing short channel effect and optimized power consumption, thesearchitectureshaverepresentedabetterscalabilitythanplanarbulkandSOIdevicesandtherefore,arethepromisingcandidatesduringaggressiveCMOSdownscaling.Tosolvetheissuesregardingdegra-dation of carrier mobility for ultra-thin-body devices because of quantum mechanical confinement [3] and increased surfaceroughness scattering, strain engineering should be reconsidered.Including strain in the channel of multi-gate devices is a bit chal-lenging and until now, only three techniques have been reportedto make a GAA uniaxially tensile strained architecture from threedimensional suspended channels: OIS (oxidation-induced strain)[4,5] and metal gate strain [6] as local strain engineering tech- niques and finally, suspending the strainedSi NWs froma strainedsubstrate (SSDOI wafer) [7] as a global strain engineering tech-nique. In this work, we focus on OIS only to prepare suspendeduniaxially tensile strained Si NWs from bulk Si using local oxida-tion and hard mask/spacer technology to finally make GAAstrained devices. 2. Built-in tensile stress analysis in Si NW during process tomake GAA suspended uniaxially tensile strained Si NW n-MOSFET  The process flow to make   100nm wide suspended uniaxiallytensile strained triangular Si NWs with  h 110 i  direction from a(100) bulk Si wafer is described in details in an earlier work [5].Fig. 1 represents the summary of this process to finally make aGAA n-MOSFET architecture together with the evolution of built-in stress during the important steps while Fig. 2 represents the ac-tual suspended Si NWs after each step.About zero initial biaxial strain value ( e i ) was found in the at-tached Si NWs to the substrate (a Si rib). Suspending the Si NWusing isotropic dry Si etching temporarily induces a huge amountof tensile strain ( e Si—HM ) up to 2.6% by in-plane lateral elongationas well as possible out-of-plane buckling perhaps due to relax- 0167-9317/$ - see front matter    2009 Elsevier B.V. All rights reserved.doi:10.1016/j.mee.2009.11.024 *  Corresponding author. Tel.: +41 21 693 7356; fax: +41 21 693 3640. E-mail address:  Mohammad.Najmzadeh@epfl.ch (M. Najmzadeh).Microelectronic Engineering 87 (2010) 1561–1565 Contents lists available at ScienceDirect Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee  ations of tensile stress in the Si 3 N 4  hard mask across the Si NW aswell as on the pads close to the anchor parts. Heatingup the waferto reach the oxidation temperature diminishes a significantamount of this temporary strain by  a  factor ( a  >  1) due to visco-elastic relaxation of stress in the thin film layers of the hard maskathightemperatureaswellasgeometricalreconfigurationoftheSiNW during oxidation. Thermal oxidation at high temperature in-duces a biaxial tensile stress into the Si NW, called growth strain( e  g  ), due to lattice expansion during oxidation. The increase inthe level of tensile strain will be continued during cooling downthe wafer to room temperature due to mismatch on thermalexpansion coefficient of Si and SiO 2 . The corresponding inducedbiaxial tensile strain to the Si NW is called thermal strain ( e th ). Asmall accumulation of tensile strain in suspended Si nano-beams,called  e OIS—SF , is also reported in Ref. [8] due to possible injectionof self-interstitial Si atoms during oxidation to the oxidation front.However, as reported in Ref. [9], this strain value cannot exceed0.012% after consumption of e.g. 90% of the thickness of 50 l mlong Si beams. Therefore, the nominal value of tensile strain inthe Si NW after the oxidation step can be calculated by: e  xx  þ e  yy  ¼  e i  þ e Si—HM a  þ  b ð e  g   þ e th Þ þ e OIS—SF  ð 1 Þ The grown ring of oxide under the Si NW(see Fig. 1) may also helptoinducemorelateraluniaxialtensilestrainthanexpectedtotheSiNW due to the upward vertical forces during oxidation and duringcooling down causing consideration of a  b  factor ( b P 1).AccordingtoRef.[5],actualstrainmeasurementsontheSiNWswith the tensile hard mask on top after the oxidation step repre-sent saturation of the tensile strain to about 0.5–0.6% because of restriction on mechanical displacement of the Si NW due to dou-bly-clamped design (restriction on lateral in-plane elongation)and the tensile hard mask (restriction on out-of-plane displace-ment) causing storage of mechanical potential energy in the SiNW during the oxidation step. During stripping the hard maskand the grown oxide, the sources of strain because of hard mask,growth and thermal strain disappear [5] but the Si NW elongatesmore to release the stored mechanical potential energy causingan increase by 3–5 factor in the strain level of the Si NW (for850  C oxidation temperature; see Fig. 3 for details). At this stage,the lateral uniaxial tensile strain in the Si NW can be calculatedby: e  xx    e  xx  þ e  yy  ¼  e i  þ e OIS—SF  þ e OIS-pot  ð 2 Þ where  e OIS-pot  represents the increase in strain during the strippingstep because of the stored mechanical potential energy duringoxidation.After this stage, we believe that the possible further change inthe strain level of the Si NW after the further thin film depositionandetchingsteps (e.g. LTO, poly-Si) canbeontheorder of thepos-sibleerrorsduetotheprocessvariationfromwiretowireandfromruntorunandalsonegligibleincomparisonto2.6GPastresspeak,obtained after the stripping step. Similar thermal properties of poly-Si gate and Si NW also can avoid accumulation of thermalstress during or after gate stack deposition. Isolation of substrate(LTO dep., CMP,LTO etch)Hard maskgrowth/depositionSi rib definition(DWL, Si dry etch)Making undercut(oxidation, oxide etch)Protect the side wallsof the rib by Si3N4dep./etchIsotropic Si etch tosuspend Si wiresSacrificial oxidationStrip hard mask &grown oxideMake the gate stack(SiO2, n+ poly-Si)Gate definition (litho.and poly-Si etch)S & D n+ implantationMetallizationSiN 34 SiO 2 SiStress(Si NW)0suspended Si NW Fig. 1.  Built-in Strain analysis during the process flow to make GAA uniaxiallytensile strained Si NW n-MOSFET from bulk Si. The black arrows represent tensilestress in Si. The red arrows represent restrictions on out-of-plane mechanicalbuckling because of tensile hard mask. The blue arrow represents upward verticalforcesbecauseofthegrownringofoxideundertheSiNW.(Forinterpretationofthereferencestocolourinthisfigurelegend,thereaderisreferredtothewebversionof this article.) Fig. 2.  SEM pictures of comparable three parallel suspended 20 l m long Si NWs on three wafers after different process steps: a tensile hard mask on top before oxidation(left), after oxidation (middle) and after thestripping step(right), representing reproducibilityand controllabilityof the local straintechnique ona singlewafer as well as ondifferent wafers. 0510152000.511.522.533.544.5    T  e  n  s   i   l  e  s   t  r  e  s  s   (   G   P  a   ) L ( µ  m)   after suspending (temporary)after oxidation − 850after stripping oxide − 850after stripping oxide − 1050 0510152000.511.522.5 (1)(2)    T  e  n  s   i   l  e  s   t  r  a   i  n   (   %   ) Fig. 3.  Variation of tensile stress level (the peak of stress along Si NWs) vs. wirelength) after wet oxidation at 850  C (1) and after stripping the hard mask and thegrown oxide (2). To get highly strained Si NWs after the stripping step, theoxidation should be performed below  T   g  ð SiO 2 Þ ¼  960  C [5].1562  M. Najmzadeh et al./Microelectronic Engineering 87 (2010) 1561–1565  3. Strain characterization using micro-Raman A micro-Raman spectroscopy setup with 0.2cm  1 nominal res-olution was employed to directly measure stress along and acrossthe Si NWs at 20  C by 43.5MPa nominal stress resolution. A laserbeam with 514.5nm wavelength was focused on the Si NW anddue to having a penetration depth (762nm) higher than the thick-ness of the Si NW (  100nm), two peaks from both non-strainedbulk Si and strained Si NW were detectable in the Raman spectra.A fitting procedure with 0.07cm  1 nominal resolution (corre-spondingto15MPastressresolution)wasusedtoextracttheplaceof the two peaks in the spectra and finally, the shift in the wave-number ( D x ) was translated to tensile stress by: r  xx  þ r  yy  ½ GPa  ¼  D x  ½ cm  1  4 : 596  ð 3 Þ Line scanning along and across the Si NWs as well as area mappingwas used to find out the peak of stress along each Si NWafter eachprocess step and finally, provide comparable inputs for furtherbuilt-in stress analysis. 4. Electrical characterization of GAA suspended uniaxially tensile strained Si NW n-MOSFET  Similar strained Si NWs, fabricated earlier from low doped  6  10 16 cm  3 p-type bulk Si using the same process with oxida-tion at 1000  C, were used for micro-Raman and electrical charac-terizationsafterisolation,gatestackgrowth/deposition(SiO 2 /poly-Si), implantation and metallization steps. The electrical character-ization was carried out at room temperature by wafer probe test-ing using a Microtech Cascade probe station and an HP 4155BSemiconductor Parameter Analyzer.Fig. 6 represents normalized transfer and transconductancecharacteristics of thebendeddeviceinFig. 4 withthestress profilein Fig. 5, versus a non-bended one. According to the figure, the enhancements in normalized  I  D  and normalized transconductanceare up to 38% and 50%, respectively. As it is shown in Fig. 6, theboth enhancements decrease by increasing overdrive voltage( V  GS    V  T  ). It is worth mentioning that the observed 0.19V down-shift in the threshold voltage of the strained device is due to thestrain-induced change in the electron affinity, band gap and va-lence band density of states of the Si channel [10].The extracted low field mobility using  I  D =  ffiffiffiffiffiffi   g  m p   method [11,12]represents 53% enhancement in average electron mobility, for thestraineddeviceincomparisontothenon-strainedone. Duetohav-ing one (100) face and two slanted non-well defined faces in thetriangular GAA Si NW n-MOSFET and by considering the fact thatthe highest possible electron mobility enhancement belongs to(100) surface n-MOSFET under  h 110 i  uniaxial tensile strain [1],the highest possible local electron mobility enhancement due tostraininthetriangular GAAstructureis calculatedusingtheactualstrain profile, directly measured using micro-Raman spectroscopythrough the gate stack, in Fig. 5 and an experimental curve includ-ing electron mobility enhancement factor for (100) surface n-MOSFET vs.  h 110 i  uniaxial tensile strain in [13], representing apeak of 54% enhancement in nominal local electron mobility, andafterward, plotted in Fig. 7 (curve B). However, the experimentalelectron mobility of the suspended architecture represents even10% more than the average of our highest possible local mobilityenhancement expectation due to uniaxial tensile strain because Fig. 4.  SEM picture of a GAA Si NW n-MOSFET (left); cross-section of the GAA triangular wire close to one of its anchors (right). 012345600.10.20.30.40.50.60.70.8    T  e  n  s   i   l  e  s   t  r  e  s  s   (   G   P  a   ) x ( µ  m)L g =3.65 µ  m 012345600.10.20.30.40.5    T  e  n  s   i   l  e  s   t  r  a   i  n   (   %   ) Fig. 5.  Stress profile along the 5 l m long Si NW presented in Fig. 4 after the gatestack deposition step. Fig. 6.  Transfer and transconductance characteristics of strained and non-strained5 l m long Si NW devices at  V  DS  ¼  50mV (the smaller  W  eff   corresponds to thestrained device). For the strained device:  V  T   ¼  0 : 0384V, SS=64mV/dec; for thenon-strained device:  V  T   ¼ þ 0 : 1525V, SS=66mV/dec. M. Najmzadeh et al./Microelectronic Engineering 87 (2010) 1561–1565  1563  of local volume inversion and corner effect [14], possible higherelectronmobilityenhancement factorthanexpectedduetohavingalowerdopinglevelinourwaferincomparisontotheuseddopinglevelin[13],possiblecross-sectionvariationalongthechannelandparallel operation of a parasitic MOSFET via the bulk [15]. Finally, by considering the positive contribution of all the mentioned elec-tronmobilityboosterstogetherforthesuspendedarchitecture,theactuallocalelectronmobilityalongthechannelofthesuspendedSiNW is plotted in Fig. 7 showing a peak of 64% mobility enhance-ment (curve C) in comparison to the non-strained device. 5. Discussion The shorter wires fabricated from this bulk top-down platformare thicker because of the pattern dependency of the isotropic Sietchingprocessandtherefore,lessstrainedduetotheirhighercrit-ical load for buckling. To scale down this local stressor technique,the isotropic Si etching step, used to suspend the wires from bulk,should be prolonged to thin down the shorter wires to e.g. 300nmbeforetheoxidationstepto finallyget e.g. 50nmthickSi NWafterthe sacrificial oxidation step. This solution offers strained Si NWswithshorterlengthsbutlessvariationinthewirelengthispossibleonawaferduetoconsumingallthelongerSiNWsintheSietchingand the sacrificial oxidation steps (see Fig. 8).The suspended uniaxially tensile strained Si NWs can be alsofabricated using a SOI top-down Si NW platform to immuneagainst the pattern dependency of the process. In this platform,due to defining the first wire shapes by e-beam lithography butnot spacer technology/isotropic Si etching, the initial thicknessand the width of the wires before the oxidation step are indepen-dent of the wire length. In this case, performing a short sacrificialoxidation can accumulate mechanical potential energy to the SiNWs that can be released in a stripping step. Simple calculationsshow that the critical load for buckling of a 2 l m long and 10nmthick Si NW fabricated from the SOI platform is the same as a20 l mlong and 100nmthick Si NWfabricated fromthe bulk plat-form with e.g. 2.6GPa peak of tensile stress and perhaps, a similarstress peak can be obtained in the newSi NW( r cr  ¼  p 2 3    E     t L   2 [9]; E  : Young’s modulus;  t  : thickness;  L : length). However, severalparameters e.g. percentage of oxidation of the Si NW, oxidationconditions, etc. also influence the value of the stored mechanicalpotential energy and therefore, should be taken into account asthe parameters that can even optimize the final strain value inthe Si NW after the stripping step.Another approach to make scaled devices is making a short de-viceonlyatthestrainpeakregionoftheSiNWusingLTOtoisolatethe substrate, open uponly the middle part of the wire andfinally,gate stack deposition, implantation and metallization (see Fig. 9). 012345300350400450500550600  ABCDE ×  1.43 ×  1.53 ×  1.64 ×  1.54      µ    0    (  x   )   (  c  m    2    /   V .  s   ) x ( µ  m) Fig. 7.  Local mobilityenhancementalongthechannel: Tri-gatenon-strainedSi NW(A); effect of local tensile strain on local mobility (nominal) (B); actual localmobility along the suspended channel (C); average of nominal local mobility alongthe channel (D); found experimental mobility in the GAA suspended Si NW n-MOSFET (E). Fig. 8.  TheSi NWswithstrainpeaks representedinFig. 3afterthestrippingstep(up); theSiNWsafterabout 25%prolongationof theisotropicSi etchingstepandafterwardthe same oxidation and stripping steps (bottom). After this prolongation, the shorter wires are buckled more, validating the scalability potential of the local oxidationtechnique. However, the longer wires were consumed completely during the etching and oxidation steps and therefore, less variation in wire length is possible on a singlewafer. LG n+DLTOSBulk Si (p-type) Al-Sipoly-Si Fig. 9.  Device implementation with short channel length centered on the Si NWregion with a peak of e.g. 2.6GPa lateral uniaxial tensile stress.1564  M. Najmzadeh et al./Microelectronic Engineering 87 (2010) 1561–1565  6. Conclusion Local oxidation accompanied by hard mask technology wasused as a local stressor technology to induce local lateral uniaxialtensile stress up to 2.6GPa to the suspended Si NWs, fabricatedusing a bulk top-down Si NW platform. The strained Si NWs wereprocessed further to provide GAA uniaxially tensile strained de-vices. Two strained and non-strained Si NWs were electricallycharacterized and the actual strain profile, measured directly onthe electrically characterized GAA Si NW via poly-Si using micro-Raman spectroscopy, was used to extract local mobility enhance-ment along the channel.  Acknowledgment The authors thank K.E. Moselund and V. Pott for the enlightendiscussions. This work is partially funded by the Nanosil Europeannetwork of excellence (FP7). References [1] M. Chu et al., Annual Review of Materials Research 39 (2009) 203.[2] K. Ota et al., Tech. Digest IEDM 27 (2002).[3] K. Uchida et al., Tech. Digest IEDM 633 (2001).[4] K.E. Moselund et al., Tech. Digest IEDM 191 (2007).[5] M. Najmzadeh et al., Microelectronic Engineering 86 (2009) 1961.[6] N. Singh et al., Electron Device Letters 28 (2007) 558.[7] P. Hashemi et al., ECS Transactions 16 (2008) 57.[8] A.M. Pyzyna et al., MEMS 189 (2004).[9] A.M. Pyzyna, Thermal Oxidation-induced Strain in Silicon Nanobeams, Ph.D.Thesis, UCSB, 2005.[10] J.S. Lim et al., IEEE Electron Device Letters 25 (2004) 731.[11] G. Ghibaudo, Electronics Letters 24 (1988) 543.[12] G. Ghibaudo, Microelectronic Engineering 39 (1997) 31.[13] S.E. Thompson et al., Tech. Digest IEDM 1 (2006).[14] K.E. Moselund et al., ESSDERC 359 (2006).[15] V. Pott et al., IEEE Transactions on Nanotechnology 7 (2008) 733. M. Najmzadeh et al./Microelectronic Engineering 87 (2010) 1561–1565  1565
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