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Multi-gate Si nanowire MOSFETs: Fabrication, strain engineering and transport analysis

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Multi-gate Si nanowire MOSFETs: Fabrication, strain engineering and transport analysis
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  POUR L'OBTENTION DU GRADE DE DOCTEUR ÈS SCIENCESacceptée sur proposition du jury:Dr C. Dehollain, président du juryProf. M. A. Ionescu, directeur de thèseProf. S. Mantl, rapporteur Dr J.-M. Sallese, rapporteur Prof. A. Schenk, rapporteur Multi-gate Si nanowire MOSFETs: Fabrication, strain engineering and transport analysis THÈSE N O  5507 (2012)ÉCOLE POLYTECHNIQUE FÉDÉRALE DE LAUSANNE PRÉSENTÉE LE 2 NOVEMBRE 2012 À LA FACULTÉ DES SCIENCES ET TECHNIQUES DE L'INGÉNIEURLABORATOIRE DES DISPOSITIFS NANOÉLECTRONIQUESPROGRAMME DOCTORAL EN MICROSYSTÈMES ET MICROÉLECTRONIQUESuisse2012 PAR Mohammad NAJMZADEH   Acknowledgements  As a first step, I would like to thank Swiss Federal Institute of Technology in Lausanne-EPFL,the EDMI doctoral school and the Nanoelectronic Devices Laboratory (Nanolab) for doing  this thesis in a competitive basis. It was a good opportunity to gain several knowledge in this thesis supported by extensive course works in microsystems and microelectronics as well,organized by EPFL, FSRM and MEAD Education SA. Thanks to Dr. Yoshishige Tsuchiya and Sheng Ye at Southampton University, UK, for the micro-Raman measurements (using a TERS setup) on deeply scaled cross-section Si nanowires and Dr. Di Wang and Dr. Robby Prang at Karlsruhe Institute of Technology (KIT), Germany, for the HRTEM cross-sections on my  nanowires with 0.08 nm resolution. Thanks to Dr. Per-Erik Hellstrom at KTH Royal Institute of  Technology, Stockholm, Sweden, for the poly-Si/SiO 2  gate stack, Dr. Sarah Olsen at Newcastle University, UK, for the micro-Raman measurement on sub-100 nm wide nanowires and Dr.Jean-Michel Sallese at EPFL to support the parameter extraction part of this thesis in theexperiment, modeling and simulation steps. Thanks to Dr. Wladek Grabinski and Dr. DidierBouvet (Dr. Paul Salet, Dr. Dimitrios Tsamados and Dr. Suyat Ayoz as well) for organizing the group meetings and providing feedbacks on the process, the electrical characterizationand the simulation steps. Thanks to Matthieu Berthomé, for helps on the transport analysissteps in my nanowires, used for the three recent IEEE TED paper submissions (#1-3), andthe other Ph.D. students, post-docs, all the secretaries and staff at Nanolab and EPFL for the happy moments. Fabrication of bulk Si nanowires was pretty challenging, especially the isolation step, needing several process monitoring to minimize the process variation. Thanks to the CMi staff for the extensive technical supports during the various process steps, especially regarding several process issues for the first SOI Si nanowire run-card at EPFL including an ALD high-k/metal- gate stack. Note that we could fabricate the GAA sub-5 nm cross-sectional Si nanowiressuccessfully and with 100% efficiency from our only two SOI wafers, dedicated to validatemy first SOI Si nanowire run-card. Thanks to Mir-Enterprise Ltd., UK, and the Philips clean room at Eindhoven, the Netherlands, for performing the high-k/metal-gate ALD gate stack on mt 100 mm SOI wafers including suspended sub-5 nm cross-sectional Si nanowires. It was a pretty difficult task, performing all the steps in a few hours while monitoring and checking the actual process steps by EPFL at the same time as well. All the works went smoothly and with the highest possible quality and efficiency, only by perseverance, hardworking, precision and organizationduringtheexperiments,electricalcharacterization,publicationandinternational conference presentations.iii   Acknowledgements I would like to thank Prof. Andreas Schenk, the head of Nano-Device Physics Group at SwissFederal Institute of Technology in Zurich-ETHZ, Dr. Jean-Michel Sallese from STI Scientistsgroup at Swiss Federal Institute of Technology in Lausanne-EFPL, Prof. Adrian M. Ionescu,the head of Nanoelectronic Device Laboratory at Swiss Federal Institute of Technology inLausanne-EFPL, the thesis director, Prof. Siegfried Mantl from Forschungszentrum Julich GmbH research center, Juelich, Germany, and finally, Dr. Catherine Dehollain, from the RFICgroup, Swiss Federal Institute of Technology in Lausanne-EFPL, the jury director, for the highinternational level Ph.D. examination covering simulation, modeling and technology aspects in a competitive basis. Performing the Ph.D. thesis at EPFL was an excellent opportunity to gain several experiences and knowledge on even the topics that I was not working directly considering various paperreview requests from IEEE Transactions on Electron Devices (TED) and Institute Of Physics (IOP) e.g. Nanotechnology during my Ph.D. at EPFL. Thanks also to the Swiss National Science Foundation (SNSF) for the financial support to perform this project as well.iv    Abstract Multi-gate devices e.g. gate-all-around (GAA) Si nanowires and FinFETs are promising can-didates for aggressive CMOS downscaling. Optimum subthreshold slope, immunity against short channel effect and optimized power consumption are the major benefits of such archi- tectures due to higher electrostatic control of the channel. On the other hand, Si nanowiresshow excellent mechanical properties e.g. yield and fracture strengths of 10 ± 2% and 30 ± 1%in comparison to 3.7% and 4.0% for bulk Si, respectively, a strong motivation to be used asexclusive platforms for innovative nanoelectronic applications e.g. novel strain engineering techniques for carrier transport enhancement in multi-gate 3D suspended channels or lo-cal band-gap modulation using  > 4 GPa uniaxial tensile stress in suspended Si channels toenhance the band-to-band tunneling current in multi-gate Tunnel-FETs, all without plastic deformation and therefore, no carrier mobility degradation in deeply scaled channels. In this thesis and as a first step, a precise built-in stress analysis during local thermal oxidation of suspended Si NWs in the presence of a Si 3 N 4  tensile hard mask was done. Accumulation of up to 2.6 GPa uniaxial tensile stress in the buckled NWs is reported. The contribution of hard mask/spacer engineering on the stress level and the NW formation was studied and buckled self-aligned dual NW MOSFETs on bulk Si with two sub-100 nm cross-sectional Si coresincluding  ∼ 0.8 uniaxial tensile stress are reported. Micro-Raman spectroscopy was widely  used in this thesis to measure stress in the buckled NWs on both bulk and SOI substrates.  A process flow was designed to make dense array of GAA sub-5 nm cross-sectional Si NWsusing a SOI substrate including a high level of stress. The NW stress level can be engineered simply usinge.g. metal-gate thinfilmstress suitable for bothNMOS andPMOS devices. Lately, highly and heavily doped architectures with a single-type doping profile from source to drain, called junctionless and accumulation-mode devices, are proposed to significantly simplify the fabrication process, address a few technical limitations e.g. ultra-abrupt junctions in orderto fabricate shorter channel length devices. Therefore, in this process flow, a highly doped accumulation-mode was targeted as the operation mechanism. Finally, extensive TCAD device simulation was done on GAA Si NW JL MOSFETs to study the corner effects on the device characteristics, from subthreshold to strong accumulation,report the concept of local volume accumulation/depletion, quantum flat-band voltage, significant bias-dependent series resistance in junctionless MOSFETs and finally, support the experimental data to extract precisely the carrier mobility in sub-5 nm Si NW MOSFETs. keywords: Si nanowire, multi-gate, stressor, mobilityenhancement, micro-Raman, TCADsimulation,nano-transport,ALDgatestack,accumulation,inversion,junctionless. v 
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