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Local volume depletion/accumulation in GAA Si nanowire junctionless nMOSFETs

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Local volume depletion/accumulation in GAA Si nanowire junctionless nMOSFETs
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  IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 12, DECEMBER 2012 3519 Local Volume Depletion/Accumulation in GAA SiNanowire Junctionless nMOSFETs Mohammad Najmzadeh, Student Member, IEEE  , Jean-Michel Sallese, Matthieu Berthomé, Student Member, IEEE  ,Wladek Grabinski, Senior Member, IEEE  , and Adrian M. Ionescu, Senior Member, IEEE   Abstract —In this paper, we report, for the first time, cornereffect analysis in the gate-all-around equilateral triangular siliconnanowire (NW) junctionless (JL) nMOSFETs, from subthresholdto strong accumulation regime. Corners were found to accumulateand deplete more electrons than the flat sides or the channelcenter, when above (local accumulation) and below (local deple-tion) the flat-band voltage, respectively. On the contrary to thecorner effect in the inversion mode (IM) devices, there is nomajor contribution of corners in the subthreshold current, andtherefore, there is no subthreshold device behavior degradation(only one threshold voltage in the system). N-type channel dopinglevels of 1 × 10 19 , 5 × 10 18 , and 1 × 10 18 cm − 3 were used forquasi-stationary device simulations of JL and AM MOSFETs, andcorner effect was studied for 5, 10, and 15 nm wide equilateraltriangular Si NW MOSFETs with a 2 nm SiO 2 gate oxide thick-ness ( V   DS = 0 V; T  = 300 K). While the local quantum andclassical electron density peaks are located in the corner re-gions above the flat-band voltage, reducing the channel dopingand the channel cross-section was found to slightly suppress thenormalized total accumulation electron density per unit length, N  acc t / (CW eff  ) , in strong accumulation regime.  Index Terms —Accumulation mode (AM), corner effect, gate-all-around (GAA), junctionless (JL), local accumulation, localdepletion, quantum confinement, Si nanowire (NW), 3-D TCADSentaurus Device simulation. I. I NTRODUCTION M ULTI-GATE architectures such as gate-all-aroundnanowires and FinFETs are promising candidates foraggressive CMOS downscaling, due to an almost optimizedsubthreshold slope, immunity against short channel effects, andoptimized power consumption. Recently, highly and heavilysingle-type doped Si devices along the source–channel–drain,called accumulation mode (AM) and junctionless (JL), havebeen proposed [1], [2]. These devices present a simpler fab-rication method to overcome some technical limitations of  junction-based devices like ultra-abrupt junctions, which are Manuscript received May 23, 2012; revised August 7, 2012; acceptedSeptember 7, 2012. Date of publication October 19, 2012; date of currentversion November 16, 2012. This work was supported by the Swiss NationalScience Foundation. The review of this paper was arranged by Editor K. Roy.M. Najmzadeh, M. Berthomé, W. Grabinski, and A. M. Ionescu arewith the Nanoelectronic Devices Laboratory, Swiss Federal Instituteof Technology in Lausanne (EPFL), 1015 Lausanne, Switzerland(e-mail: mohammad.najmzadeh@epfl.ch; matthieu.berthome@epfl.ch;wladyslaw.grabinski@epfl.ch; adrian.ionescu@epfl.ch).J.-M. Sallese is with the STI Scientists Group, Swiss Federal Instituteof Technology in Lausanne (EPFL), 1015 Lausanne, Switzerland (e-mail: jean-michel.sallese@epfl.ch).Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/TED.2012.2220363 issues for ultra short channel devices. The multi-gate architec-tures (except circular cross-sections that can be obtained byhydrogen annealing [3] or stress-limited oxidation [4]) havecorners (e.g., see [5]–[9]). Therefore, an in-depth analysis of the corner effect on the electrical characteristics of the multi-gate devices is necessary. In this paper, we report, for the firsttime, corner effect analysis of the GAA Si NW JL nMOS-FETs using a GAA equilateral triangular Si NW architecture(2 nm SiO 2 gate oxide thickness; V  DS = 0 V; T  = 300 K). Thecorner effect analysis was done from subthreshold to strongaccumulation, considering various channel doping levels (1 × 10 18 –1 × 10 19 cm − 3 ) and channel cross-sectional dimensions(5–15 nm Si NW width).To make a clear corner effect study in GAA Si NW JLMOSFETs with minimized short channel effects on the devicecharacteristics, 40 nm long channel architectures were usedfor the simulations ( > 6 times longer than the natural lengthof the widest NW; see, e.g., [10]). This is a first step tomake a precise device and transport analysis in multi-gateJL architectures with short channel lengths including corners(see e.g., [11]). Note that various Si NW cross-sections canbe experimentally achievable using bottom-up [12], [13] orSi NW sidewall engineering by anisotropic Si etching in top-down [6], [14] platforms. In this paper, we only concentrateon the equilateral triangular cross-sections, due to having thenarrowest corner angle among the symmetrical architectures.In this paper and as a first step, we investigate the cornereffect through the local and total electron densities in thechannel cross-section (with and without channel quantization)using a 15 nm wide Si NW MOSFET at various channel dopinglevels. Afterward, the effect of channel dimension shrinkage ina JL MOSFET at a fixed channel doping level will be studied indetails.II. N UMERICAL S IMULATION TCADSentaurusDevice(G-2012.06)wasusedforthequasi-stationary numerical simulation of GAA Si NW MOSFETs.Considering electrostatic and quasi-Fermi potential equations,the local carrier densities in a 3-D structure can be extracted ateach bias voltage. The electrostatic potential for the classic caseis the solution of the nonlinear Poisson equation ∇· (  ∇ ψ ) = − q  ( − n + p + N  + D ) (1)where q  , n , p , and N  + D are electron charge, electron density,hole density, and ionized donor concentration, respectively 0018-9383/$31.00 © 2012 IEEE  3520 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 12, DECEMBER 2012 Fig. 1. Equilateral triangular GAA Si NW MOSFET and its cross-section. (ionized acceptor concentration is neglected in our case). Toinclude the 3-D quantization effects in nanoscale, the densitygradient quantization model is coupled to the Poisson equa-tion [15], [16]. The quantum correction procedure includesmodification of the density of states [16]. The semi-classicalSlotboom bandgap narrowing model was used for the highlyand heavily doped Si channels [16], [17]. The local carrierdensities can be computed from the electron and hole quasi-Fermi potentials, considering Fermi-Dirac statistics coveringboth degenerate and nondegenerate regimes [16].Fig. 1 shows the 3-D GAA Si NW architecture, used for thedevice simulations (gate length: 40 nm; SiO 2 gate oxide thick-ness: 2 nm). The Si NW width is set to 15 nm (equilateral tri-angle), and three channel doping levels were investigated. Thegate workfunction was set to 4.5 eV (a midgap workfunction).In all the simulations, V  DS was fixed at 0 V, to eliminate theeffect of longitudinal electric field from source–drain potentialdifference on the local electron density distribution along thechannel.III. F ROM S UBTHRESHOLD TO S TRONG A CCUMULATIONIN A 15 nm W IDE Si NW MOSFETQuasi-stationary TCAD device simulation was done on a15 nm wide Si NW MOSFET at three channel doping levels ( 1 × 10 19 , 5 × 10 18 , and 1 × 10 18 cm − 3 ) . The device charac-teristics can be studied using local electron density distributionin the channel at each gate voltage as well as charge on the gateversus gate voltage characteristics ( Q G – V  GS , can be obtaineddirectly from the simulations).  A. Operation of AM/JL MOSFETs The JL and AM MOSFETs, unlike the typical inversion-mode (IM) MOSFETs, do not have any p-n junction, and thechannel doping level is nominally determining the device type(heavily doped devices, > 1 × 10 19 cm − 3 , called JL) [1]. Bothdevices have the same operation mechanism, while here, weprovide a brief explanation on this mechanism for a simpleplanar single-gate AM/JL nMOSFET.Below the threshold voltage, the channel is fully depleted,while the majority of the subthreshold current is passingthrough the channel volume (the closer to the channel–dielectric interface, the more depletion). There can be differentdefinitionsofthresholdvoltage.Whereasasimpleextrapolationwas proposed in [18], in this paper, we will adopt a slightly dif-ferent condition. Assuming a full depletion approximation, our Fig. 2. Normalized quantities of  N  t , dN  t /dV  GS , d 2 N  t /dV  2GS , and Q G with respect to the maximum values versus V  GS for the GAA 15 nm wideSi NW MOSFET at 1 × 10 19 cm − 3 channel doping including quantumconfinement. The maximum values for each parameter are 5.46 × 10 7 cm − 1 ,4.48 × 10 7 cm − 1 · V − 1 ,1.29 × 10 8 cm − 1 · V − 2 ,and7.35 × 10 − 12 C · cm − 1 ,respectively. threshold voltage condition can be approximated when creatinga neutral region at the middle of the fully depleted channel (thecorresponding local electron density almost equals the channeldoping).Thecurrentpassingthroughtheneutralregioniscalledbulk current. Applying a higher gate voltage extends the neutralregion causing an increase in the bulk current.The flat-band condition will be reached when the entirechannel cross-section is neutral, implying that the bulk currentwill saturate at this point. Applying a higher gate voltage leadsto the creation of an accumulation layer close to the channel-dielectric interface. Therefore, the drain current includes onefixed (saturated bulk current) and one variable (accumulationcurrent) component. Note that the V  FB – V  TH can be engi-neered by channel doping, gate oxide thickness, channel cross-sectional geometry, and dimension.  B. Threshold Voltage Extraction Method  The threshold voltage can be extracted from the peak of thesecond derivative of the total electron density per unit length ( N  t ) versus gate voltage [19] (similar to the transconductancechange method [20]), while N  t can be calculated by integratingthe electron density over the channel cross-section and at themiddle of the channel ( x = L G / 2 ; L G equals gate length) N  t =    n ( y,z ) dydz. (2)Fig. 2 shows the total electron density per unit length andthe corresponding derivatives (normalized to the correspondingmaximum values) for a GAA 15 nm wide Si NW MOSFETdoped at 1 × 10 19 cm − 3 , including quantum confinement. C. Flat-band Voltage Extraction Method  In a standard planar MOSFET, the flat-band voltage isthe gate voltage for which the electrostatic potential is beingconstant in the entire channel cross-section. However, due tothe quantum confinement, the flat-band condition cannot bereached in the entire channel cross-section for a certain gate  NAJMZADEH et al. : LOCAL VOLUME DEPLETION/ACCUMULATION IN GAA Si NW JL nMOSFETs 3521 TABLE IK EY D EVICE P ARAMETER E XTRACTION F ROM THE Q UASI -S TATIC D EVICE S IMULATIONS OF THE GAA 15 nm W IDE Si NW MOSFETs AT D IFFERENT C HANNEL D OPING L EVELS voltage when including corners. Nevertheless, we can stilldefineaneffectiveflat-bandvoltagefortheentirechannelcross-section(or quantumflat-bandvoltage )asakeydeviceoperationparameter which can be approximated from the x -interceptof the Q G – V  GS curve as a first step (called V  1 Q FB ), a directoutput result from the presented gate charge– V  GS quasi-staticsimulations.While the flat-band condition can be reached in the entirechannel cross-section when discarding quantization, even in thecorners, the observed slight difference between the actual flat-band voltage ( V  C  FB ) and the extracted one from the Q G – V  GS curve forthe classiccase, V  1 C  FB − V  C  FB ,can be usedtojustifytheflat-band voltage extraction method mismatch when quantumeffects cannot be neglected. This slight inaccuracy, observedto be below a 13 mV range in Table I, is mainly due to thehigher electron density in the channel parts close to the sourceand drain, as well as to the parameter extraction methodology.Based on this remark, we can estimate the effective flat-bandvoltage for the entire device ( V  Q FB or V  C  FB ).Note that the flat-band condition may not be reached in theentirechannelcross-sectionevenfortheclassiccase.Thiscouldbe due to some local effective bulk doping concentrations in thecorners,asreportedpreviouslyinthesubthresholdregimeoftheIM devices to describe the local threshold voltage downshiftin the corners [19], [21]. However, perhaps a much narrowercorner angle is needed to significantly affect the local flat-bandvoltage variation between the corner and the side.  D. Gate–Channel Capacitance and Effective Channel Width Due to the quantization-based gate–channel capacitance [22]and effective channel width shrinkages in GAA NWs, insteadof extracting each parameter separately, the CW eff  parameter,the product of the gate-channel capacitance and the channelwidth, is introduced. This parameter can be extracted from thefirst derivative of the total electron density per unit length ( N  t ) versus the gate voltage in strong accumulation regime CW eff  ( V  GS ) = ( dN  t /dV  GS ) · q. (3)The CW maxeff  values, reported in Table I, are extracted at V  GS = 1.500 V for all structures.  E. Key MOSFET Parameters at Different Channel Doping Levels Fig. 3 shows the second derivative of the total electrondensity per unit length ( d 2 N  t /dV  2GS ) versus V  GS for the GAA Fig. 3. d 2 N  t /dV  2GS versus gate voltage for the GAA Si NW MOSFETs atvarious doping levels with or without quantization (QE or CE, respectively). 15nmwideSiNWMOSFETsforthreechanneldopingconcen-trations, considering classical and quantum effects. The resultsreported in Table I show that the quantization is upshiftingboth the threshold and the flat-band voltages, due to the higherquantized subband energies [9], [23], [24]. Note that, evenfor the heavily doped structure and on the contrary to the IMdevices [19], there is no hump effect below the gate voltagecorresponding to the main peak in the d 2 N  t /dV  2GS versus V  GS curve, thus representing a unique threshold voltage in thesystem. The hump appearing above the threshold voltage of the heavily doped device in the classical simulation is due tothe nonlinear operation of bulk regime between the thresholdand the flat-band voltages as well as creation of accumulationconduction paths in the channel, reported before for the planarAM devices [2].IV. L OCAL E LECTRON D ENSITY D ISTRIBUTION A CROSSTHE C HANNEL F ROM S UBTHRESHOLDTO S TRONG A CCUMULATION Figs. 4 and 5 show the quantum electron density (QED)and classical electron density (CED) in the cross-section of a GAA 15 nm wide Si NW JL MOSFET (channel doping:1 × 10 19 cm − 3 ) in subthreshold, above threshold, and strongaccumulation regimes. According to the figures, the majorityof electrons are accommodated in the corner regions only instrong accumulation. To study better the bias-dependent chargedistribution mechanism in the channel cross-section, local QEDand CED profiles as functions of gate voltage are plotted along y = 0 (see e.g., Fig. 4) in Fig. 6. This provides a wide range of information on the local electron density variation in the corner,side, and volume.The maximum and minimum of the local CEDs in accu-mulation and depletion regimes are both occurring on the SiNW–dielectric interface, respectively. Therefore, a simple wayto study the effect of corners on the local electron densityvariation can be the local CED corner to side ratio at dif-ferent channel doping and gate voltages. Note that, due tothe quantization effects, the peak of QED occurs inside thechannel volume. Fig. 6 inset shows this classical ratio as afunction of  V  GS – V  FB . According to this figure (as well as fromthe local CEDs at different channel doping levels in Fig. 7),  3522 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 12, DECEMBER 2012 Fig. 4. Cross-sectional QED at the middle of a GAA 15 nm wide Si NW JL MOSFET for three operation regimes (oxide is not shown; channel doping:1 × 10 19 cm − 3 ). (Left) Subthreshold ( V  GS = − 0.200 V ) . (Center) Above threshold ( V  GS = 0.100 V ) . (Right) Strong accumulation ( V  GS = 1.500 V ) .Note that V  Q TH = 0.027 V and V  Q FB = 0.399 V.Fig. 5. Cross-sectional CED at the middle of a GAA 15 nm wide Si NW JL MOSFET for three operation regimes (oxide is not shown; channel doping:1 × 10 19 cm − 3 ). (Left) Subthreshold ( V  GS = − 0.200 V ) . (Center) Above threshold ( V  GS = 0.100 V ) . (Right) Strong accumulation ( V  GS = 1.500 V ) .Note that V  C  TH = 0.025 V and V  C  FB = 0.360 V. corners accumulate more electrons in comparison to the side inaccumulation regime ( > V  FB ) , while they deplete also furtherbelow the flat-band voltage.  A. Origin of Local Depletion/Local Accumulation in AM/JL MOSFETs The different corner effects and device behavior in the IMand the AM/JL MOSFETs come from a distinct conductionmechanism, surface versus volume conduction in differentregimes, as well as conduction of minority versus majoritycarriers. Analyzing the effect of corners on the carrier densitydistribution in the channel cross-section is not simple. Ac-cording to the simulations, it strongly depends on the channelgeometry, doping level, and dielectric thickness (see e.g., [19],[25]–[27]). There is no clear geometrical definition of thecorner region, while the analysis becomes even more complexincluding quantization.The surface conduction by minority carriers is the onlyconduction mechanism in the IM devices, while the AM/JLMOSFETs exhibit surface conduction above V  FB and volumeconduction below V  FB , both involving majority carriers. Dueto having a maximized surface to volume ratio in the cornerregion in comparison to the side region, the surface conductionmechanisms (above V  FB for the AM/JL, all operation regimesfor the IM devices) should provide a higher local mobilecharge density in the corner region (local volume inversionor local volume accumulation in the IM and the AM/JLdevices, respectively). On the other hand, reduction of the localeffective channel doping in the corners because of side gatesand the effective body thickness reduction in the corners weresuggested previously to describe the local threshold voltagedownshift and the local volume inversion in the corners of theIM devices in subthreshold regime as well [21].Due to having a smaller effective channel body thicknessin the corner region in comparison to the side, the volumeconduction mechanism in the corner region is expected to beminimized with respect to the side region below the flat-bandvoltage, since the volume of corner is negligible. Therefore,no subthreshold conduction path in the corner regions of theAM/JL MOSFETs is expected to emerge from I  D – V  GS charac-teristics, as already observed in Fig. 3 (no hump below the mainpeak of the d 2 N  t /dV  2GS versus V  GS curves).  B. Corner Effects on Global Accumulation Electron Densitiesin Accumulation Regime To assess corner effects on the global device characteris-tics, the normalized total accumulation electron density perunit length in the entire channel cross-section is defined as ( V  GS > V  FB ) N  acc t ( V  GS ) = N  t ( V  GS ) − N  t ( V  FB ) . (4)  NAJMZADEH et al. : LOCAL VOLUME DEPLETION/ACCUMULATION IN GAA Si NW JL nMOSFETs 3523 Fig. 6. Local (top) QED and (bottom) CED profiles across the 15 nm wideNW channel volume at different V  GS values (from subthreshold to strongaccumulation; step: 0.100 V) at N  d = 1 × 10 19 cm − 3 (cut at y = 0; see e.g.,Fig. 4). The inset shows local CED corner to side ratio from subthreshold tostrong accumulation. Fig. 8 shows how this normalized accumulation electron den-sity varies with respect to the gate voltage for the 15 nm wideSi NW MOSFETs, with three different channel doping levelsat V  GS > V  FB . In order to study the effect of quantization andchannel cross-sectional variation for various devices, accumu-lation electron densities are normalized to CW eff  ( V  GS ) at eachbias voltage (see also Section V-A). According to Fig. 8, thenormalized total accumulation electron density above the flat-band voltage is increasing with the channel doping, while allthe normalized values are slightly below the ideal limit that canbe calculated as follows: N  acc t ( V  GS ) / [CW eff  ( V  GS )] = ( V  GS − V  FB ) /q. (5)Therefore, corners clearly cannot be considered as CMOSboosters. Note that the local CED corner to side ratio is in-creasing by channel doping reduction in accumulation regime(Fig. 8 inset). On the other hand and from Fig. 8, heavily dopedstructures represent a higher normalized total accumulationelectron density per unit length and reveal characteristics closerto the ideal case, reflecting a more uniform distribution of thelocal electrons in the cross-section. This could be explained byelectrostatic screening increase at higher doping levels in accu-mulationregime.Inallcases,thenormalizedtotalaccumulationelectron density per unit length is slightly degraded by quantumconfinement as well. Fig. 7. Local CED profiles across the 15 nm wide Si NW channel volumeat different gate voltages (from subthreshold to strong accumulation; step:0.100 V) for (top) N  d = 5 × 10 18 cm − 3 and (bottom) 1 × 10 18 cm − 3 . Theplots correspond to the cut at y = 0.Fig. 8. Normalized total accumulation electron density per unit length versus V  GS – V  FB at various channel doping levels including both quantum andclassical electrons. The normalization factor is CW eff  ( V  GS ) . The inset showslocal CED corner to side ratios in accumulation regime. V. C ROSS -S ECTIONAL S HRINKAGE AND C ORNER E FFECT In this section, GAA equilateral triangular Si NWMOSFETs with 5 and 10 nm NW widths were simulatedat a 1 × 10 19 cm − 3 channel doping level (2 nm SiO 2 gateoxide thickness). The second derivative of  N  t ( d 2 N  t /dV  2GS ) versus gate voltage curves are plotted in Fig. 9, and theextracted device parameters are reported in Table II (the
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