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Local stressors to accommodate 1.2 to 5.6 GPa uniaxial tensile stress in suspended gate-all-around Si nanowire nMOSFETs by elastic local buckling

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Local stressors to accommodate 1.2 to 5.6 GPa uniaxial tensile stress in suspended gate-all-around Si nanowire nMOSFETs by elastic local buckling
  ISDRS 2011, December 7-9, 2011, College Park, MD, USAISDRS 2011 – Student Paper Local Stressors to Accommodate 1.2 to 5.6 GPa Uniaxial Tensile Stress inSuspended Gate-All-Around Si Nanowire nMOSFETs by Elastic Local Buckling M. Najmzadeh, D. Bouvet, W. Grabinski, A. M. Ionescu   Swiss Federal Institute of Technology (EPFL), Nanolab, Lausanne, Switzerland,  Multi-gate architectures such as gate-all-around (GAA) Si nanowires are the promising candidates for aggressive CMOS downscaling due to the immunity   to the issues regarding short channel effect,improved subthreshold slope and optimized power consumption. On the other hand, Si nanowiresrepresent excellent mechanical properties e.g. yield strength of 10±2% [1] in comparison to 3.7% for bulk Si [2], a strong motivation to be used as interesting exclusive platforms for innovative nanoelectronicapplications e.g. novel strain engineering techniques for carrier transport enhancement in multi-gate 3Dsuspended channels [3]-[5] or local band-gap modulation using >4 GPa uniaxial tensile stress insuspended Si channels to enhance band-to-band tunneling current in multi-gate Tunnel-FETs [6], allwithout plastic deformation and therefore, no carrier mobility degradation in deeply scaled channels.In this paper, we demonstrate the integration of local oxidation [3] and metal-gate strain [4]technologies to induce 3.3%/5.6 GPa uniaxial tensile strain/stress in 2 µm long suspended Si nanowireMOSFETs, the highest process-based stress record in MOSFETs until now , by elastic local buckling. Fig.1 represents the fabrication process to make GAA uniaxially tensile strained Si nanowire MOSFETs froma 100 mm (100) Unibond SOI substrate with 1×10 18 cm -3 phosphorous channel doping. Highly dopedaccumulation-mode was chosen as the operation regime to mainly simplify the process in nanoscale [7].Dry oxidation of the Si nanowires with a tensile Si 3  N 4 hard mask on top at 925 °C helps to accumulatemechanical potential energy in the nanowires due to in-plane/out-of-plane elongation/bending restrictionsduring the oxidation process [3]. This stored mechanical potential energy will be released in the form of mechanical buckling after stripping the hard mask, the grown oxide and the nanowire detachment fromthe BOX layer. The high-k/metal-gate stack step includes 5 nm ALD HfO 2 , RTA (600 °C, 15 min) andfinally, 50 nm TiN by sputtering at 25 °C including -2.0 GPa biaxial compressive intrinsic thin filmstress. The thin film stress in the metal-gate layer can be engineered by sputtering power, thickness anddeposition temperature [4]. The metal-gate thin film with an intrinsic compressive stress tends to stretch,causing further elongation/buckling of the suspended Si nanowires. Gate pattern, S/D implantation,metallization and sintering are the further process steps.Employing micro-Raman spectroscopy to measure stress in GAA deeply scaled SOI Si NWs with ahigh-k/metal-gate stack is pretty challenging due to the non-transparency of the metal-gate and on theother hand, low level of Raman signal from deeply scaled NWs in comparison to the strong backgroundRaman signal from the Si carrier wafer. Therefore, top and tilted-view SEM micrographs were used toestimate the stress level in the NWs, instead of micro-Raman spectroscopy. Fig. 1 represents the top-viewSEM micrograph of a buckled array of 2 µm long Si NWs with the represented TEM cross-section. Theactual maximum NW deflection is calculated based on the observed maximum in-plane and out-of-planedeflections. Afterward, by considering a symmetric Gaussian buckling profile along the NWs ( ɳ  =1 µm, σ =0.5 µm, see Fig. 2) and assuming a uniform strain profile along the NWs, the expected elongation iscalculated from the arc-length of the buckled NWs and afterward, the stress values vs. NW widths arereported in Fig. 3 (assuming Si Young’s modulus of 169 GPa). It is worth mentioning that the local stresscan be even higher in the case of a non-uniform stress profile along the NWs [3], can be detected only bymicro-Raman spectroscopy. As Fig. 3 represents, the narrower NWs have a higher buckling, mainly dueto a smaller critical-load-for-buckling value. Therefore, the NW width modulation, from 44 to 4 nm, leadsto a significant uniaxial tensile stress modulation in NWs, from 1.2 to 5.6 GPa, respectively, on a singlewafer, providing room for further potential applications while impossible by global stressors e.g. [5].Electrical characterization was done using a Cascade prober and a HP 4155B Semiconductor Parameter Analyser at room temperature. Fig. 4 represents transfer and transconductance characteristicsof a GAA MOSFET with the TEM cross-section in Fig. 1, including 10 triangular <110> Si NWs withW top ~4 nm, under 5.6 GPa uniaxial tensile stress at different V DS . The threshold voltage and low-fieldelectron mobility in the accumulation-regime were extracted using transconductance change [8] and  ISDRS 2011, December 7-9, 2011, College Park, MD, USAISDRS 2011 – I D /g m0.5 [9] methods, respectively, yielding low-field electron mobility of 332 cm 2 /V · s at V DS =100 mV.This corresponds to 32% electron mobility enhancement in comparison to non-strained bulk Si at thesame doping level [10], due to the uniaxial tensile stress in the channel. The electron mobilityenhancement can be even higher up to ~100% at >~2 GPa uniaxial tensile stress [11] using excellentchannel-dielectric interface. I on /I off  ratio is also ~10 5 at V DS =1.500 V.In conclusion, the highest process-based stress record in MOSFETs is represented by elastic local buckling using top-down Si NWs. Significant stress level modulation in the channel from 1.2 to 5.6 GPaon a single wafer is demonstrated for the first time by varying the NW width. The GAA Si NW MOSFETwith 5.6 GPa uniaxial tensile stress is characterized and the electron mobility enhancement is reported.This work is supported by Swiss National Science Foundation (SNSF). Thanks to EPFL-CIME for TEM lamella preparation and TEM observation. References [1] T. Kizuka, Y. Takatani, K. Asaka, R. Yoshizaki, “Measurements of the atomistic mechanics of single crystalline silicon wiresof nanometer width”, Physical Review B, vol. 72, p. 035333, 2005.[2] K. E. Petersen, “Silicon as a mechanical material”, Proceedings of IEEE, vol. 70, pp. 420- 457, 1982.[3] M. Najmzadeh, L. De Michielis, D. Bouvet, P. Dobrosz, S. Olsen, A. M. Ionescu, “Silicon nanowires with lateral uniaxialtensile stress profiles for high electron mobility gate-all-around MOSFETs”, Microelec. Eng., vol. 87, pp. 1561-1565, 2010.[4] N. Singh et al, “Observation of metal-layer stress on Si nanowires in gate-all-around high- κ  /metal-gate devicestructures”, IEEE Electron Device Letters, vol. 28, pp. 558-561, 2007.[5] P. Hashemi, L. Gomez, M. Canonico, J. L. Hoyt, “Electron transport in Gate-All-Around uniaxial tensile strained-Si nanowiren-MOSFETs”, International Electron Devices Meeting, IEDM 2008., pp.1-4, 15-17 Dec. 2008.[6] M. Najmzadeh, K. Boucart, W. Riess, A. M. Ionescu, “Asymmetrically strained all-silicon multi-gate n-Tunnel FETs”, SolidState Electronics, vol. 54, pp. 935-941, 2010.[7] J. P. Colinge et al, “Nanowire transistors without junctions”, Nature Nanotechnology, vol. 5, pp. 225-229, 2010.[8] H.S. Wong, M. H. White, T. J. Krutsick, R. V. Booth, “Modeling of transconductance degradation and extraction of thresholdvoltage in thin oxide MOSFET's”, Solid-State Electronics, vol. 30, pp. 953-968, 1987.[9] G. Ghibaudo, “New method for the extraction of MOSFET parameters”, Electronics Letters, vol. 24, p. 543, 1988.[10] R. Hull, “Properties of crystalline silicon”, INSPEC, 1 st ed., 1999.[11] M. Chu, Y. Sun, U. Aghoram, S. E. Thompson, “Strain: A solution for higher carrier mobility in nanoscale MOSFETs”,Annual Review of Materials Research, vol. 39, pp. 203-229, 2009. (100) Unibond SOISOI doping (P:1e18 cm -3 )SiO 2 /Si 3  N 4 hard mask dep.HSQ-NW pattern by EBLDry hard mask and Si etchDry oxidation, 925°C, 7 hSuspend naked Si NWs bywet Si 3  N 4 and SiO 2 etchHfO 2 /TiN gate stack dep.Gate patternS/D doping (P: 2e20 cm -3 )Metallization (AlSi-1%)Sintering 200 nm CarbonBOXTiNGAA Si NWSixNyTiN  ) 2 /(2   )    G  a  u  s  s   i  a  n   b  u  c   k   l   i  n  g  p  r  o   f   i   l  e   (  µ  m   ) x(µm)W=30 nmW=40 nmW=50 nmW=60 nmy(x)=A  e +B Fig. 1: Process flow (left), a dense array of elastically buckledGAA Si NWs with 5.6 GPa uniaxial tensile stress in thechannel and a triangular cross-section (W top ~4 nm) (right).Fig. 2: Symmetric Gaussian buckling profiles along2 µm long GAA Si nanowires with different initialmask nanowire widths. 30405060050100150200250    M  a  x   i  m  u  m   d  e   f   l  e  c   t   i  o  n   (  n  m   ) W mask (nm)0123456    U  n   i  a  x   i  a   l   t  e  n  s   i   l  e  s   t  r  e  s  s   (   G   P  a   ) 3040506002040    A  c   t  u  a   l   N   W   w   i   d   t   h   (  n  m   ) W mask (nm) - -12 10 -11 10 -10 10 -9 10 -8 10 -7 10 -6 10 -5 T=298 K    I    D    (   A   ) V GS (V)V DS =0.100 VV DS =1.500 VSS=106 mV/dec. -10120. DS =0.100 V   gm   ID    I    D    (  µ   A   ) ,  g   m    (  µ   S   ) V GS (V) Fig. 3: Maximum deflection and uniaxial tensile stress level inthe buckled Si NW vs. NW width on the mask. The insetshows actual NW width vs. mask NW width.Fig. 4: Transfer and transconductance characteristicsof a GAA nMOSFET with 5.6 GPa uniaxial tensilestress in the NWs (V TH =0.70 V at V DS =100 mV).
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