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Gate-all-around buckled dual Si nanowire nMOSFETs on bulk Si for transport enhancement and digital logic

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Gate-all-around buckled dual Si nanowire nMOSFETs on bulk Si for transport enhancement and digital logic
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  Gate-all-around buckled dual Si nanowire nMOSFETs on bulk Si for transportenhancement and digital logic M. Najmzadeh a, ⇑ , Y. Tsuchiya b , D. Bouvet a , W. Grabinski a , A.M. Ionescu a a Nanoelectronic Devices Laboratory, Swiss Federal Institute of Technology (EPFL), CH-1015 Lausanne, Switzerland b Electronics and Computer Science, University of Southampton, Southampton SO17 1BJ, United Kingdom a r t i c l e i n f o  Article history: Received 4 October 2012Received in revised form 30 January 2013Accepted 4 February 2013Available online 13 February 2013 Keywords: Multi-gateSi nanowireLocal oxidationStrained SiMicro-Raman spectroscopyTransport enhancementLogic a b s t r a c t Inthispaper, wereportformationof GAAbuckleddual SinanowireMOSFETsincludingtwosub-80nmSicores onbulkSiusing0.8 l moptical lithographyandlocal oxidationfor thefirsttime. 0.833GPauniaxialtensile stress is measured in the buckled suspended dual Si nanowires using micro-Raman spectroscopy.The array of GAA buckled dual Si nanowire MOSFETs at  V  DS  =50mV shows 64mV/dec. subthresholdslope and 61% stress-based low-field electron mobility enhancement in comparison to the omega-gaterelaxed reference device. Finally, digital logic implementation is demonstrated using multi-gate nano-wires on bulk Si.   2013 Elsevier B.V. All rights reserved. 1. Introduction Multi-gate architectures e.g. gate-all-around (GAA) Si nano-wires (NWs) and FinFETs are promising candidates for aggressiveCMOS downscaling due to the immunity against short channel ef-fects, optimized subthreshold slope and low power consumption[1]. Stress is being used for the 90nm technology nodes and be-yond to enhance the carrier mobility while downscaling as well[2].InducingstresstotheGAAsuspendedSiNWchannelsisatech-nological challenge and only a fewtechniques are reported [3–10].In this paper, we report a process to make GAA uniaxially tensilestrained dual NWs including two sub-80nm Si cores on bulk Siusing 0.8 l m optical lithography, local oxidation and hard mask/spacertechnologyforthefirst time. Thisisafirstclearsteptointe-gratelocal stressors inthe 3Dstackof suspendedFins andSi nano-wires [11–15] in GPa level as CMOS boosters for analog and digitalCMOS applications. 2. Fabrication Fig. 1showstheprocessflowtomakeGAAbuckleddual Si NWson bulk Si (100mmp-type prime (100) wafer, 0.1–0.5 X .cmusing0.8 l m optical lithography, SiO 2  hard mask and spacer technology.Starting with the prior nominal reported process in [15] but usingtaller Fins in step 1 (>1.5 l mhigh insteadof   1.1 l m) would yieldtoobtaintwocompletelyseparatedSicores,withsub-80nmcross-sections, right after the oxidation step in step 3. This is due to ahigher oxidation rate of the Si side-walls in comparison to thetop (100) Si surface, built-in stress in the growing SiO 2  thin filmduring this oxidation process and complete consumption of theSi bridge between the two Si cores in such an aggressive wet oxi-dation process (850  C, 8.3L/min O 2 , 16.0 L/min H 2 ) in taller Fins.Note that the Si NW cross-section dimension can be engineeredusing various Si Fin height and width before oxidation (step 1), SiFin side-wall slope engineering by Si dry etching methodology(step 1; see e.g. [9]), the SiO 2  spacer thickness on the Si Fin side-walls(step2)andfinally,oxidationtemperatureandduration(step3). In step 3, local oxidation in the presence of a hard mask on topof the Si NWs at 850  C (below glass transition temperature of SiO 2 ; 960  C) leads to inducing uniaxial tensile stress in the sus-pended NWs [6]. The level and type (compressive or tensile) of stressinsuch3Dchannelscanbeengineeredsimplybymetal-gatethin film stress (using a high-k/metal-gate stack) [3], oxidationtemperature [6] and residual thin film stress type (compressiveor tensile) and level in the hard mask [6,15].GAA Si NWs fromboth W0.8 and W1.0 NWs are obtained usingan optimized isolation step (LTO etching and CMP) in comparisonto [15] while omega-gate devices, attached to the substrate, wereobtained from W1.2 NWs (or wider initial mask NW width; see 0167-9317/$ - see front matter    2013 Elsevier B.V. All rights reserved.http://dx.doi.org/10.1016/j.mee.2013.02.003 ⇑ Corresponding author. Tel.: +41 21 693 5633; fax: +41 21 693 3640. E-mail address:  Mohammad.Najmzadeh@epfl.ch (M. Najmzadeh).Microelectronic Engineering 110 (2013) 278–281 Contents lists available at SciVerse ScienceDirect Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee  Fig. 3). Notethat thegate stackstepincludes15nmof SiO 2  growthby dry oxidation at 850  C followed by 230nm of LPCVD N + in situdoped poly-Si deposition (phosphorous: 2  10 20 cm  3 ) andannealing to activate the dopants. This is mainly to have a uniformheavily doped poly-Si gate around the 3Dchannels to suppress thepoly-Si gate depletion issues and therefore, to obtain the bestzdevice characteristics especially in subthreshold regime (see e.g.[16]).The gate pattern was done to cover the entire of the Si NW re-gion (see Fig. 2 – left), mainly to diminish the contribution of thenakedSi NWonbothchannelsidesintheseriesresistance.Thisef-fect would be more significant while downscaling the NW cross-section, reported before in [15]. This would allow to compare theelectrical characteristics of various devices with different cross-section dimensions easier. 3. Stress measurement using micro-Raman spectroscopy  Due to the broad poly-Si Raman spectra, can cover the crystal-line Si and strained Si spectra, Raman scan was done on the nakedNWextension of the finalized devices (Fig. 2 – right) instead of viapoly-Si gate. Therefore, similar devices to the ones in Section 4(10 l m NW length, Fig. 2 – left) were chosen but with a shortergate length to access the NW extension directly. Fig. 4 shows theRaman spectra, using 532nm laser wavelength (  1 l m penetra-tion depth in Si) to obtain both strained NW and relaxed bulk Siunderneath spectra. Using the Lorentzian peak fitting to obtainthe peaks of strained Si NW and relaxed bulk Si [15,17], we reportaccumulation of +0.833GPa uniaxial tensile stress in the finalizedbuckledW0.8 dual NWMOSFETs, mainly due to the oxidationstepin the presence of hard mask. The wider W1.0 NW shows a prettysmaller stress (<+100MPa) due to the higher critical-load-for-buckling value [6] while the W1.2 device is stress free (attachedto the substrate). 4. Electrical characterization and key MOSFET parameters The multi-gate MOSFET array devices (with SEM tilted-view inFig. 2 – left and cross-sections in Fig. 3) were characterizedusing a Cascade prober and a Semiconductor Parameter Analyzer at 293Kand  V  BS =0V (grounded substrate). The NWs are aligned to the < 110 >  orientation to obtain the highest stress-based electronmobility enhancement [18]. The normalized transfer characteris-tics at  V  DS  =0.050 and 1.000V are plotted in Fig. 5 (left-bottomaxes; normalization factor: C ox  W eff  ).The threshold voltages are extracted using the transconduc-tance change [19] method, quasi-independent of series resistanceand conduction mechanism, and are reported in Table 1. Thelow-fieldelectronmobilityvaluesforthemulti-gateNWswereex-tracted using the Y-function method [15–21], quasi-independentof series resistance and mobility attenuation factor. Almost 2 3W0.8 W1.0 W1.211.5 µm4 5 G S DSiSiO 2 Poly-Si AlSi-1%   GLTO Fig. 1.  Process flow to make GAA suspended uniaxially tensile strained dual Sinanowires with two sub-80nm Si cores on a bulk Si substrate using 0.8 l mopticallithography. W0.8 represents the initial 0.8 l m mask nanowire width. GAA dual Si NWsPoly-Si 200 nm Pt 400 nm Poly-SiPtGAA NW 400 nm PtPoly-SiSiLTO Fig. 3.  SEM nanograph cross-section of W0.8 (top-left), W1.0 (top-right) and W1.2(bottom) Si nanowire MOSFETs on bulk Si. 4 󰂵m Poly-SiLTOSDG AlSi-1% 1 󰂵m Poly-SiRaman scanLTOSG Fig. 2.  An array of GAA buckled dual NW MOSFET (left). A dual Si NW MOSFETincluding two sub-80nm Si cores with a shorter gate length than the NW length,used for stress measurement by micro-Raman spectroscopy (right). Fig. 4.  Stress measurement on a buckled suspended dual Si NWMOSFET (see Fig. 2– right) using micro-Raman spectroscopy. M. Najmzadeh et al./Microelectronic Engineering 110 (2013) 278–281  279  optimum subthreshold slopes at  V  DS  =50mV, high  I  on / I  off   ratios at V  DS  =1.000V (  10 7 , if tuning  V  TH ) and low leakage current in100fA range in Fig. 5 in all the three devices reflect an excellentgate stack. The GAA buckled dual NWMOSFET shows 61% electronmobility boost and up to 65% normalized transconductanceenhancement in strong inversion in comparison to the non-strained omega-gate MOSFET (Fig. 5, right-top axes), mainly dueto uniaxial tensile stress. Note that up to  100% electron mobilityboost can be achieved further, including >  2GPa uniaxial tensilestress in the channel [18]. 5. Low voltage digital logic implementation on a bulk Si NW platform In this section, we implement the simplest digital logic (NMOSinverter) using the bulk Si NW platform, without adding any addi-tional step to the process flow in Fig. 1. Due to the threshold volt-age engineering possibility (sign change; see Table 1) on the samewafer, without additional processes e.g. channel implantation, it isfeasible to have both enhancement-mode ( V  TH  >0, EM) and deple-tion-mode ( V  TH  <0, DM) loads on the same wafer. Therefore, it ispossible to significantly engineer the voltage gain e.g. above unityeven having identical load and driver on a single wafer. Note thatthe threshold voltage reduction, and sign change, by cross-sectionshrinkage is due to volume inversion, corner effect and uniaxialtensile stress [26,27].NMOS logic, in contrary to CMOS, consumes power while thedriver is in the ’’ON’’ state but a necessary logic for some semicon-ductors e.g. CdS and CdSe, which suffers from unipolarity and thustechnicallyarenotpossibletomakecomplementaryinverters[24].III-V materials also show a high electron mobility suitable for highspeed/low voltage digital circuit applications but suffering from avery low hole mobility, causing a non-promising performance fora complementary architecture [25]. Parallel to the application of suchNMOSlogicengineeringinnon-Sidevices,addressingintegra-tion of CMOS boosters, e.g. stressors in GPa level, for furtherenhancement on static and dynamic response of low power/lowvoltage CMOS logic devices on a GAA Si nanowire platform[22,23] is the further clear step in this direction. 5.1. Electrical characterization of NMOS inverters Fig. 6 shows the top-view SEM micrograph of a NMOS inverter.Each inverter (W0.8, W1.0 and W1.2) has nominally identical loadand driver (the same NW length, width and gate length). The elec-trical characterization was carried out at 293K using a Cascadeprober and a HP 4155B Semiconductor Parameter Analyzer. Fig. 7shows the voltage transfer characteristics (VTC) of the multi-gateMOSFETs (W0.8, W1.0 and W1.2), all at  V  DD  =0.400V. The W0.8NMOSinverterhastheDMarchitecture, duetoitsnegativethresh-old voltage, while the others have the EM architecture. Accordingto the figure, it is clear that the scaled devices showa more abrupttransition behavior. The DM architecture is providing the highestvoltage gain, the largest output voltage swing and the lowest out-put voltage while the driver is in the ‘‘ON’’ state. The observedcharacteristics can be described by small-signal and staticanalyses. 5.2. Small-signal analysis of multi-gate NW NMOS inverters Considering the small-signal model of the NMOS devices [28]for both load and driver in saturation regime and in the transitionregion of the logic gate, the voltage gain of the multi-gate sus-pended dual NW logic in the DM architecture equals:  A v   ¼   g  md   ð r  od k r  ol Þ    g  md    r  od = 2  ð 1 Þ where  g  md  is the transconductance of the driver. The  r  od  and  r  ol  aretheoutputresistancesofthedriverandload,respectively,assumingalmost similar in this section. For the multi-gate suspended NWlo-gic in the EM architecture:  A v   ¼   g  md   ð 1 =  g  ml k r  od k r  ol Þ    g  md =  g  ml  ð 2 Þ where g ml  is the transconductance of the load. Finally, for the ome-ga-gate logic in the EM architecture:  A v   ¼   g  md   ð 1 =  g  ml k 1 =  g  mbl k r  od k r  ol Þ  ð  g  md =  g  ml Þ  ð 1 = ð 1 þ g ÞÞ ð 3 Þ where  g  mbl  is the body effect transconductance of the load and g  =  g  mbl /  g  ml .Having almost identical load and driver transistors, the voltagegain for the EM suspended NW inverter should be around unityand for the EM omega-gate devices should be slightly smaller -1.0 -0.5 0.0 0.5 1.010 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 10 4    I    D    /   (   C   o  x  .   W   e   f   f    )   (   A .  m   /   F   ) V GS (V) W0.8 W1.0 W1.2-1.0 -0.5 0.0 0.5 1.00255075100125150175200V DS =1.000 VV DS =0.050 VV DS =0.050 VV BS =0 V55%   g   m    /   (   C   o  x  .   W   e   f   f    )   (   S .  m   /   F   ) V GS -V TH (V)65% Fig. 5.  Normalizedtransfer(left-bottomaxes)andtransconductancecharacteristics(right-top axes) of W0.8, W1.0 and W1.2 MOSFETs (normalization factor:  C  ox  W  eff  ).  Table 1 Key MOSFET parameters of multi-gate NW MOSFETs at  V  DS =50 mV,  V  BS =0 V and T   = 293 K (  : The contribution of each Si core in the dual NW architecture). V  TH  (V) SS (mV/dec)  W  eff   (nm)  l 0  (cm 2 /V  s)W0.8   0.030 64 464 (398/66)  565W1.0 0.150 67 1060 393W1.2 0.198 69 1580 351 5 µm GND VDDG1LTOOutputG2LoadDriver Poly-Si AlSi AlSiInput Fig. 6.  SEM microgragh of a NMOS inverter (W0.8). The nanowire length and gatelength are 12.0 and 2.0 l m, respectively.280  M. Najmzadeh et al./Microelectronic Engineering 110 (2013) 278–281  due to the body effect. According to Eq. 1, the voltage gain for theDM architecture can be higher than unity. Suspending the NWfrom bulk removes the body effect, causing a more abrupt transi-tioninthe EMarchitecture.It is worthmentioningthat thevoltagegain for the omega-gate device was found to be higher than unityonly at  V  DD P 1.4V, due to the body effect. 5.3. Static analysis of multi-gate suspended NMOS inverters Fig. 8 shows the key logic parameters of the multi-gate sus-pendedNWs(W0.8andW1.0) onbulkSi atdifferent powersupplyvoltages. Transition width (TW= V  iH  V  iL  ) and logic swing(LS= V  oH  V  oL  ) are plotted vs.  V  DD  for both devices. According tothis figure, the DMarchitectureshows a narrowertransitionwidthand a higher logic swing (>69%  V  DD ). On the other hand, the EMarchitecture shows a wider transition width (<31% of   V  DD ) and asmaller logic swing (<30% of   V  DD ). Note that the multi-gate sus-pendedSi NWDMshowsafairyhighDCloadresistance, becomingevenhigherby V  DD  whilethemulti-gatesuspendedSi NWEMloadDC resistance is much smaller, reducing even further by  V  DD  (6.6–17.5M X  vs. 870–183k X  at  V  DD  =0.400–1.200V, respectively; allreported at  V  i  =1.000V). Finally, the high bias-dependency of themaximum voltage gain of the W0.8 device is reported in Fig. 8-in-set, feasible to achieve also a higher voltage gain (e.g.   35 byincreasing  V  DD  to 1.200V), even having identical load and driver,by the DM architecture while the EM device shows an almost con-stant voltage gain peak over a wide  V  DD  range. 6. Conclusion An array of GAA buckled dual Si NW MOSFETs including>0.8GPa uniaxial tensile stress is fabricated on Bulk Si using0.8 l m optical lithography and local oxidation. The stress-basedlow-fieldelectronmobilityenhancement inthebuckledNWsisre-ported in comparison to the relaxed multi-gate device. Finally,multi-gate digital logics are implemented using this bulk Si NWplatform,reportingahighvoltagegaintunabilityonasinglewafer.  Acknowledgments Thanks to Dr. Per-Erik Hellström, KTH Royal Institute of Tech-nology, Stockholm, Sweden, for the gate stack step. This work issupported by Swiss National Science Foundation. References [1] K.J. Kuhn, IEEE Trans. Electron Dev. 59 (2012) 1813–1828.[2] M. Chu et al., Ann. Rev. Mater. Res. 39 (2009) 203–229.[3] N. Singh et al., IEEE Electron Dev. Lett. 28 (2007) 558–561.[4] M. Li et al., IEEE IEDM (2007) 899–902.[5] K.E. Moselund et al., IEEE IEDM (2007) 191–194.[6] M. Najmzadeh et al., Microelectron. Eng. 86 (2009) 1961–1964.[7] M. Najmzadeh et al., Microelectron. Eng. 84 (2010) 1561–1565.[8] B. Liu et al., IEEE Electron Dev. Lett. 31 (2010) 1371–1373.[9] M. Najmzadeh et al., Solid-State Electron. 74 (2012) 114–120.[10] R.A. Minamisawa et al., Nat. Commun. 3 (2012) 1096.[11] P.C.H. Chan et al., IEEE ICSICT (2004) 81–85.[12] T. Ernst et al., IEEE IEDM (2006) 1–4.[13] K. Buddharaju et al., Solid-State Electron. 52 (2008) 1312–1317.[14] R.M.Y. Ng et al., IEEE Electron Dev. Lett. 30 (2009) 520–522.[15] M. Najmzadeh et al., IEEE Nanotechnol. 11 (2012) 902–906.[16] K.E. Moselund et al., Microelectron. Eng. 85 (2008) 1406–1409.[17] I.D. Wolf et al., Semicond. Sci. Technol. 11 (1996) 139–154.[18] M. Chu et al., Ann. Rev. Mater. Res. 39 (2009) 203–229.[19] H.-S. Wong et al., Solid-State Electron. 30 (1987) 953–968.[20] G. Ghibaudo, Electron. Lett. 24 (1988) 543–545.[21] K.E. Moselund, M. Najmzadeh, et al., IEEE Trans. Electron Dev. 57 (2010) 866–876.[22] S.C. Rustagi et al., IEEE Electron Dev. Lett. 28 (2007) 1021–1024.[23] S. Maheshwaram et al., IEEE Electron Dev. Lett. 32 (2011) 1011–1013.[24] P. Wu et al., ACS Nano 3 (2009) 3138–3142.[25] S. Oktyabrsky, P. Ye, Fundamentals of III–V semiconductor MOSFETs, 1st ed.,Springer, 2010.[26] J.S. Lim et al., IEEE Electron Dev. Lett. 25 (2004) 731–733.[27] J.G. Fossum et al., IEEE Electron Dev. Lett. 24 (2003) 745–747.[28] P.R. Gray, P.J. Hurst, S.H. Lewis, R.G. Meyer, Analysis and Design of AnalogIntegrated Circuits, 5th ed., John Wiley and Sons, New York, 2009. Fig. 7.  Voltage transfer characteristics (VTC) of the multi-gate W0.8, W1.0 andW1.2 Si nanowire NMOS inverters (inset: absolute value of the voltage gain,  A v  j j¼  dV  o = dV  i j j , vs. input voltage). W0.8 has the DM architecture while the otherswith positive threshold voltages have the EM architecture. Fig. 8.  Transition width (TW= V  iH  V  iL  ) and logic swing (LS= V  oH  V  oL  ) vs.  V  DD  forthe multi-gate suspended (W0.8 and W1.0) Si nanowire NMOS inverters (inset:voltage gain peak vs.  V  DD ). M. Najmzadeh et al./Microelectronic Engineering 110 (2013) 278–281  281
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