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Digital Systems Design Using VHDL 3rd Edition Roth Solutions Manual
Full download: https://goo.gl/RHi4Mi
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Digital Systems Design Using VHDL 3rd Edition Roth
SOLUTIONS MANUAL
Full download: https://testbanklive.com/download/digital-systems-design-using-vhdl-3rd-edition-roth-solutions-manual/
Chapter 2 Solutions
2.1 (a)
VHDL - VHSIC Hardware Description Language VHSIC - Very High Speed Integrated Circuit
(b)
VHDL has statements that execute concurrently since it must model real hardware in which the components are all in operation at the same time.
(c)
A hardware description language allows a digital system to be designed and debugged at a higher level of abstraction than schematic capture with gates, flip-flops, and standard MSI building blocks. The details of the gates and flip-flops do not need to be handled during early phases of design. Designs are more portable when low-level library-specific details are not included in the model. HDLs allow the creation of such portable high-level behavioral models.
2.2 (a)
Legal:
A_123
,
and1
; Illegal:
123A
(Starts with number),
_A123
(starts with underscore),
A123_
(ends with underscore),
c1 c2
(adjacent underscores),
and
(reserved word).
(b)
They all equivalent. VHDL is not case sensitive.
2.3 (a)
(b)
2.4
entity
Comb
is
port
(A, B, C, D :
in
bit; Z :
out
bit);
end
Comb;
architecture
Comb2_1
of
Comb
is signal
E, F, G, H, I : bit;
begin
H <= (A
and
B
and
C)
after
5 ns; E <= H
or
D
after
5 ns; G <= (B
nor
C)
after
5 ns; F <= G
nand
A
after
5 ns; I <=
not
F
after
2 ns; Z <= E
xor
I
after
5 ns;
end
Comb2_1;
2.5 (a)
entity
one_bit_sub
is port
(x, y, bin:
in
bit; diff, bout:
out
bit);
end
one_bit_sub;
architecture
equ
of
one_bit_sub
is begin
diff <= x
xor
y
xor
bin; -- difference. See problem 1.2 answer bout <= (
not
x
and
bin)
or
(not x
and
y) or (bin
and
y); -- borrow out. See problem 1.2 answer
end
equ;
(b)
entity
four_bit_sub
is
port
(a, b:
in
bit_vector(3
downto
0); bin:
in
bit; d:
out
bit_vector(3
downto
0); bout:
out
bit);
end
four_bit_sub;
architecture
test
of
four_bit_sub
is
signal
bo: bit_vector(3
downto
0) := 0000 ; -- borrow bits
component
one_bit_sub
port
(x, y, bin:
in
bit; diff, bout:
out
bit);
end component
;
begin
FS0: one_bit_sub
port map
(a(0),b(0),bin,d(0),bo(1)); FS1: one_bit_sub
port map
(a(1),b(1),bo(1),d(1),bo(2)); FS2: one_bit_sub
port map
(a(2),b(2),bo(2),d(2),bo(3)); FS3: one_bit_sub
port map
(a(3),b(3),bo(3),d(3),bout);
end test
;
2.6 (a)
entity
circuit
is
port
(A, B, C, D:
in
bit; G:
out
bit);
end
circuit;
architecture
internal
of
circuit
is signal
E, F: bit;
begin
E <= A
and
B; F <= E
or
C; G <= D
and
F;
end
internal;
(b)
entity
circuit
is
port
(A, B, C, D:
in
bit; G:
out
bit);
end
circuit;
architecture
internal
of
circuit
is signal
E, F: bit;
begin
process
(A, B, C, D, E, F)
begin
E <= A
and
B; F <= E
or
C; G <= D
and
F;
end process
;
end
internal;
2.7
A
changes to 1 at 25 ns,
B
changes to 1 at 2
0 + ∆
ns,
C
does not change
2.8 (a)
A falling-edge triggered D flip-flop with asynchronous active high clear and set (
b)
Q = '0', because Clr = 1 has priority.
2.9
entity
SR_Latch
is port
(S, R:
in
bit; Q, Qn:
inout
bit);
end
SR_Latch;
architecture
proc
of
SR_Latch
is begin
process
(S, R)
begin
if
S = '1'
then
Q <= '1';
end if
;
if
R = '1'
then
Q <= '0';
end if
;
end process
; Qn <=
not
Q;
end
proc;
2.10
entity
MNFF
is
port
(M, N, CLK, CLRn:
in
bit; Q:
inout
bit; Qn:
out
bit);
end
MNFF;
architecture
MN
of
MNFF
is begin
process
(CLK, CLRn)
begin
if
CLRn = '0'
then
Q <= '0';
elsif
CLK = '0'
and
CLK'event
then
if
M = '0'
and
N = '0'
then
Q <=
not
Q;
elsif
M = '0'
and
N = '1'
then
Q <= '1';
elsif
M = '1'
and
N = '0'
then
Q <= '0';
elsif
M = '1'
and
N = '1'
then
Q <= Q; --optional
end if
;
end if
;
end process
; QN <=
not
Q;
end
MN;
2.11
entity
DDFF
is
port
(R, S, D, Clk :
in
bit; Q :
out
bit);
end
DDFF;
architecture
Behav
of
DDFF
is begin
process
(Clk, R, S)
begin
if
R = '0'
then
Q <= '0';
elsif
S = '0'
then
Q <= '1';
elsif
Clk'event
then
Q <= D;
end if
;
end process
;
end
Behav;
2.12 (a)
entity
ITFF
is
port
(I0, I1, T, R:
in
bit; Q, QN:
inout
bit);
end
ITFF;
architecture
behavior
of
ITFF
is begin
process
(T, R)
begin
if
R = '1'
then
Q <= '0'
after
5 ns;
else
if
(I0 = '1'
and
T = '1'
and
T'event)
or
(I1 = '1'
and
T = '0'
and
T'event)
then
Q <= QN
after
8
ns;
end if
;

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