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A Cycle Accurate NoC Simulation Framework for Early Phase Exploration of SDR Platforms

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A Cycle Accurate NoC Simulation Framework for Early Phase Exploration of SDR Platforms
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  A Cycle Accurate NoC Simulation Framework for Early Phase Exploration of SDR Platforms  Nikolaos Zompakis 1 , Martin Trautmann 2 , Alexandros Bartzas 1 , Stylianos Mamagkakis 2 , Dimitrios Soudris 1 , Liesbet Van der Perre 2 , Francky Catthoor  2  1 ECE School, National Technical Univ. of Athens, 15780 Zografou, Greece 2 IMEC vzw, Kapeldreef 75, 3001 Heverlee, Belgium   Abstract Software-defined radio (SDR) terminals are critical to enable concrete and consecutive inter-working between  fourth generation wireless access systems or communication modes. The next generation of SDR terminals is intended to have heavy hardware resource requirements and switching between them will introduce dynamism in respect with timing and size of resource requests. On the longer term, SDR terminals will be extended to become cognitive radios enabling efficient spectrum usage. This paper presents a system-level  framework combined with a cycle-accurate NoC simulation environment that enables the simulation of such complex, dynamic hardware/software SDR designs. The platform specifications are represented as a virtual architecture by a coarse-grain simulator described in SystemC that includes a set of configuration parameters. The key of our approach is that our simulator environment provides automatic wrapper tools able to explore the SDR platform parameters and simultaneously transmit the interconnection traffic in a cycle-accurate NoC simulator giving the opportunity to examine the impact of different topologies at the system bandwidth at execution time. Thus, we can do an exploration, which can pinpoint at a very early design  phase the platform component requirements for future SDR applications. This approach shows a drastic design-time reduction with the maximum possible simulation accuracy. 1.   Introduction After the introduction of the first multi-core processor chip in 2001 [3] multiprocessing has developed dramatically. Today, nearly all processor chips use multiple cores in an attempt to deliver more system performance within their  power-constrained environment. New applications such as Software Defined Radio (SDR) make usage of the additional resources offered by these MPSoC platforms. The SDR system can dynamically adopt appropriate modes to get the optimal quality of the communication service [4]. Moreover, it is widely acknowledged that early design decisions have the most significant impact on the final system performance and power consumption [5]. In this paper, we propose a simulation framework designed for SDR terminals in an early development phase. The contributions of this work are 1) the implementation of a scheduling technique as well as extraction of the bandwidth requirements at execution time 2) the development of two automatic wrappers offering automation of the whole simulation and evaluation process of different SDR  platforms. Finally, the main advantage of the work  presented in this paper is to allow a high level cycle accurate design flexibility. 2. Simulation Flow The levels that synthesize our simulation flow are shown in Figure 1.The basic implementation is separated in two abstract layers(High-Level and Low-Level) that represent the two wrappers, which are responsible for the automatic and continuous execution of our simulation flow and the storing of our simulation results. Figure 1:  Simulation Flow The functionality of each layer is shown clearly in Figure 1. Τ he high-level wrapper implements the automatic exploration of the platform parameters and the automatic run. The coarse grain SDR platform permits us to configure totally seven parameters (the number and the frequency of the processing elements, the frequency of the  communication bus, the number of antennas, the packet size, the symbol rate of the communication protocol 802.11a and the kind of the signal modulation).These  parameters create a large exploration space that requests huge effort for the designer to do it manually. For every combination of parameters in exploration space the SDR wrapper is responsible, in cooperation with a profiling tool, to trace the interconnect traffic and transfer it at run-time at the cycle accurate layer. At the cycle-accurate simulation (which in our case is  performed employing the Nostrum NoC Simulation Environment [2]) a second wrapper is accountable to analyze the traffic dimensioning (Figure 1) at execution time, synthesize the resources (based on the SDR platform  parameters of the specific exploration) and mapping them on the NoC. The mapping is performed using a bandwidth-constrained algorithm [1] to meet the platform constraints In addition the low level wrapper is responsible to configure the topology of the NoC and extract the simulation results 2.   Simulation Results Figure 2:  Simulation results of SDR platform parameters exploration on a 4x4 2D torus NoC For our simulation results, we used three basic NoC topologies (mesh, 2D and 1D torus) of 16 nodes and for each one of them we explored a series of parameters of the SDR platform. These parameters as well as their values are  presented in Array 1, constituting an exploration space of 2592 combinations. Each combination is a different SDR  platform. The evaluation of the different SDR platforms and  NoC topologies is performed through simulation and the results are presented in diagrams (due to limited space only the diagram (Figure 2) of 2D torus topology is presented). Every radius of these diagrams represents one Pareto point (and each Pareto point represents an SDR platform). The value of bandwidth for every Pareto point is at the  perimeter. The values on top of    each radius are the values that the parameters of the SDR platform must have in order to achieve that bandwidth. To enhance the readability of the diagrams the simulation results for each NoC topology are split in two diagrams. PE_Fr (MHz) Bus_Fr (MHz) Modulation #PE   #Antennas   Symbol rate (ns/OFDM_symbols) Packet Size in   Bytes  400, 600, 800 200, 400, 600 QAM16, QPSK, BPSK 2, 4, 6, 8 2, 4 1000, 1500. 2000 1000, 1500. 2000 Array 1:   SDR Exploration Space   3.   Conclusion In this paper, we present a simulation framework that can  be used at the early phase of the SDR platform design. In order to succeed the requested accuracy we combined a coarse grain with a cycle accurate simulator. The automatic exploration of the SDR platform and the interface between the two layers succeed through two wrappers, which ensure the automatic execution of our framework, and thus the automatic exploration of different SDR platforms. The design space is pruned and only the Pareto points, where each point is a different SDR platform, are presented to the designer. In this way a set of trade-offs are extracted at early design stages and presented to the designer, which is the responsible for choosing the SDR parameters and NoC topology that meets best the design constraints. The whole SDR design space exploration, NoC simulation and result visualization are completely automated through the usage of the developed wrappers thus significantly alleviating the effort of the designer. 5. References [1] S. Murali and G. D. Micheli, “Bandwidth-constrained mapping of cores onto NoC architectures,” in Proc. of  DATE.IEEE Computer Society, 2004. [2] A. Jantsch, “Models of computation for networks on chip,” in Proc. ACSD’06, pp. 165-178, 2006. [3] J. M. Tendler, J. S. Dodson, J. S. Fields, Jr., H. Le, and B.Sinharoy, “POWER4 system microarchitecture”, IBM Journal of R&D, Vol. 46, No. 1, 2002, pp. 5-26. [4] David L. Tennenhouse and Vanu G. Bose, "The Spectrumware Approach to Wireless SignalProcessing," Wireless Network .Journal, 2( 1 ),1996. [5] F. Catthoor et al., “Custom Memory Management Methodology: Exploration of Memory Organization for Embedded Multimedia System Design,” KluwerAcademic Pub., 1998.
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